CMOS SerDes or High-speed I/O, Lead Analog IC Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role Overview The Lead Analog IC Design Engineer is responsible for designing and developing analog and mixed-signal circuits- from initial concept and specification through final verification- to ensure conformance with customer requirements. Required Qualifications • At least three years of experience designing and developing CMOS SerDes or high-speed I/O integrated circuits. • Design experience with most of the following SerDes circuit blocks: Transmitters and receivers, serializers and deserializers, phase interpolators, low-jitter PLLs, high-speed clock-distribution circuits, bias circuits, and voltage regulators. • Good understanding of jitter and signal-equalization techniques. • Proficiency with CAD tools for circuit simulation, layout, and physical verification. • Master’s degree or Ph.D. in electrical engineering. • Strong problem-solving skills and analog design aptitude. • Clear written and verbal communication skills. • Ability to collaborate effectively in a team environment. Preferred Qualifications • Working knowledge of common SerDes standards and their electrical requirements. • Experience with Cadence design tools and laboratory testing. • Design experience at data rates above 10 Gbps and in process technologies below 28 nm. The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.