Design Verification Architect

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Formal Verification Architect, PCIe & UALink Controllers Role Summary We are looking for an experienced Formal Verification Architect to lead the formal verification strategy for high-performance PCIe and UALink controller IP . The ideal candidate will combine deep formal verification expertise with strong protocol and microarchitecture knowledge. This is a hands-on technical leadership role responsible for defining verification architecture, identifying high-value formal targets, solving complex proof problems, and driving formal methods throughout the IP development lifecycle. Key Responsibilities Define the formal verification architecture and methodology for PCIe and UALink controller IP. Develop block, subsystem, and end-to-end formal verification strategies spanning: Protocol engines and state machines Transaction and packet processing Flow control and credit management Ordering and dependency rules Replay, retry, recovery, and error handling Arbitration, scheduling, and resource management Power/reset and initialization sequences Configuration and control logic Identify areas where formal verification can provide stronger coverage than simulation, especially for corner cases, deadlocks, livelocks, starvation, ordering violations, data integrity, and protocol compliance . Architect assume-guarantee, compositional, abstraction, and formal decomposition strategies for large and complex controller designs.