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Silicon Roles

Design Verification Engineer

IntelUS, California, Santa Clara$105,650+Design Verification
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The published floor of $105,650 is 36% below the Design Verification median of $164,735. First seen on this site 2026-09-22, open 4 days.
Posted 2026-09-11 · read from workday

Job Details: Job Description: About Intel & Silicon Chassis Intel is seeking an Entry Level Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to the verification of next-generation interconnect and chassis IPs that underpin Intel's most ambitious SoC and platform products. Position Overview You will work alongside senior engineers to build testbenches, write constrained-random tests, close functional coverage, and root-cause simulation failures - developing end-to-end verification skills from day one. We look for engineers who think algorithmically, write clean code, and are excited to apply the latest AI-assisted development tools as a core part of how they work. You do not need to know everything on day one; you do need strong fundamentals, genuine curiosity, and the drive to ramp fast. Key Responsibilities • Develop testbench components, constrained-random stimulus, and functional checkers for interconnect and chassis IP under guidance of senior engineers • Write, run, and debug simulation tests; analyze failures and root-cause issues to closure with clear technical write-ups • Contribute to functional coverage plans, coverage closure analysis, and regression triage • Participate in spec reviews, design discussions, and bug triage; learn to contribute across architecture, design, and software boundaries • Use AI-assisted coding and debugging tools as an everyday part of development workflow; actively contribute to the team's productivity through automation and scripting • Continuously build depth in hardware design,…