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Silicon Roles

Design Verification Engineer

IntelUS, California, Santa Clara$141,910+Design Verification
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The published floor of $141,910 is exactly at the Design Verification median of $141,910. First seen on this site 2026-10-23, open 21 days.
Posted 2026-10-22 · read from workday

Job Details: Job Description: Job Description Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to verification of next-generation interconnect and chassis IPs that scale across multiple product families. You will work closely with senior engineers to build and execute robust verification plans, develop high-quality reusable environments, and help deliver first-pass silicon success through strong design verification practices. This role requires strong programming and algorithmic problem-solving skills, hands-on verification development, and willingness to work across traditional discipline boundaries. AI-assisted workflows are part of everyday development here. Responsibilities - Develop and execute verification plans and testbenches for interconnect and chassis IP/features at IP and subsystem level - Build reusable verification components, checkers, constrained-random tests, and debug infrastructure to improve coverage and productivity - Work with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute outside strict DV boundaries when needed - Analyze simulation failures, root-cause issues quickly, and drive fixes to closure with clear technical communication - Contribute to functional coverage planning, coverage closure, and quality signoff under guidance of technical leads - Contribute to both simulation and formal verification efforts; continuously improve verification automation, regression quality, and development efficiency You should also…