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Silicon Roles

Design Verification Engineer

IntelUS, California, Santa Clara$105,650+Design Verification
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The published floor of $105,650 is 26% below the Design Verification median of $141,910. First seen on this site 2026-11-12, open 1 days.
Posted 2026-11-11 · read from workday

Job Details: Job Description: About the Team Intel is building a configurable interconnect and chassis generator for SoCs and chiplets, and the Unified Intel Chassis (UIC) team is looking for an Entry Level Design Verification Engineer to be part of it. In this role, you will use simulation, formal verification, and AI-assisted development to check hardware behavior, find bugs, and build reusable verification code. Working closely with architecture, design, and tooling engineers, you will help turn specifications into working, tested hardware. We value strong fundamentals, curiosity, and engineers who follow a problem through to a solution. You will learn by building, testing ideas, and reviewing work with experienced engineers — with room to contribute to models, RTL, and tools as your skills grow. Prior industry experience is not required. Relevant experience may come from coursework, research, internships, or personal projects. Please note: This position is not eligible for Intel immigration sponsorship.