EDA Tools Software Engineer
Apply on Intel’s site →Job Details: Job Description: As a member of the PTD Litho Frame Automation Team (FRAT) in LTD (Logic Technology Development), you will be responsible for process design rule definition, construction and validation of lead certification Tape-in Collaterals for Intel's next generation process technology and products. You will be responsible for the validation and creation of VLSI layout that will enable fundamental process development. Your responsibilities will include but will not be limited to: Verify VLSI layout adherence to complex layout design rules, specifically ownership in Quality Assurance of FRAT designs across all Intel process nodes Troubleshoot design and PDK(Process Design Kit) verification issues with complex physical design flows, both industry standard and Intel tools and flows Write/update software code for cell design and testcases, verification and package design content for distribution CAD design development and support of LTD Tape-in Collateral Library for ALL Intel Process Technology nodes including CR experimental Path Finding projects Collaborating, directing, extracting, executing designs and constructs that will be used for process implementation, monitoring, improvement and development well ahead of any other team in LTD. This interaction will be with a very diverse team including Litho, Integration, Device, Test Chip, Tape Out, and OPC and RET (Reticle Enhancement Team) experts.