Skip to content
Silicon Roles

Manager, ATE Test Engineering

Astera LabsSan Jose, California, United States$195,000–$250,000Silicon Validation & Bring-up
Apply on Astera Labs’s site →
The published floor of $195,000 is 28% above the Silicon Validation & Bring-up median of $151,800. First seen on this site 2026-08-29, open 28 days.
Posted 2026-09-23 · read from greenhouse

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Manager, ATE Test Engineering to lead our Test engineering organization in San Jose, CA. This is a critical leadership role responsible for driving next-generation high-speed, high-performance products from silicon bring-up through high-volume manufacturing in advanced process nodes. Astera Labs is looking to build and scale the Test Engineering team responsible for developing scalable ATE solutions for complex mixed-signal silicon products and high-speed products that power next-generation AI infrastructure. You will shape test strategy, guide execution across wafer sort and final test, and ensure products move confidently from design through silicon bring-up and high-volume production.