Memory Silicon Validation Engineer

NVIDIA leads groundbreaking work in AI, high-performance computing, and visualization — and the memory subsystem is one of the most consequential parts of every silicon program we ship. GDDR, LPDDR, and HBM are where architecture, silicon, packaging, and manufacturing collide with reality. When memory is marginal, the whole system is marginal, and when it works, our GPUs and SoCs can hit the performance our customers depend on! We are hiring a Senior Memory Qualification Engineer inside the Silicon Co-Design Group who will own high-speed memory bring-up, characterization, and qualification on our flagship GPU, CPU and SoC programs. This is not a compliance-testing role — it is the seat where memory issues get root-caused before they become customer escapes. The two highest-leverage problems in this seat: Root-cause memory marginality before software hardens. Isolate ambiguous, cross-boundary failures across DRAM, controller, PHY, IO tuning, board, PVT, and workload — and close them with productized fixes and reusable playbooks so the next program starts from a better baseline. Build memory qualification as a repeatable, AI-accelerated capability. Every program generates large datasets of shmoo, margin, and characterization data.