PCIe Post-Silicon Validation Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are looking for a PCIe Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams. Key Responsibilities Perform hands-on PCIe post-silicon validation Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability . Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements. Drive complex issues from initial failure through root-cause analysis and final resolution . Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.