Principal Analog Design Engineer

Role Overview We are seeking an experienced Analog Design Engineer with 12-18 years of expertise in high-performance PLL and clocking solutions to join our product development team. The candidate will lead the design and development of advanced clock generation, distribution, synchronization, and timing circuits for next-generation SoCs and mixed-signal products, driving innovations from architecture definition through silicon validation and production. Key Qualifications 12+ years of experience in analog/mixed-signal IC design with strong expertise in PLL and clocking architectures. Deep transistor-level design experience of PLL building blocks including VCOs, charge pumps, phase/frequency detectors (PFDs), loop filters, clock buffers, bandgap references, current references, OPAMPs, and LDOs. Strong understanding of jitter, phase noise, clock synchronization, timing recovery, EMC/ESD, reliability, and silicon robustness. Hands-on experience with analog design and verification tools such as Cadence Virtuoso, ADE, Spectre/SPICE, and related EDA environments. Experience with silicon characterization, validation, yield improvement, and ATE characterization. Strong knowledge of advanced CMOS/FinFET technologies and analog layout considerations. Proven ability to lead technical reviews, debug silicon issues, and mentor junior engineers. Experience with high-speed SerDes, Ethernet PHYs, or timing-intensive mixed-signal systems is an added advantage.