Principal Analog IC Design Engineer, High Speed SerDes

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications. Candidate’s background should include a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development. Working knowledge of a set of common SerDes standards and their electrical requirements is a plus. Must have a thorough understanding of jitter and signal equalization techniques Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification Cadence tool experience, lab test experience, and design experience at >10Gbps and in MS or PhD in EE The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.