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Silicon Roles

Principal Engineer, Analog and Mixed-Signal DTCO

IntelUS, Oregon, Hillsboro$220,920+Analog & Mixed-Signal
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The published floor of $220,920 is 43% above the Analog & Mixed-Signal median of $154,500. First seen on this site 2026-11-10.
Posted 2026-11-09 · read from workday

Job Details: Job Description: The Group: Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) drives pathfinding and development of the analog/mixed-signal, RF, and high-speed I/O IP that defines what Intel Foundry's leading-edge process technologies can deliver. The AMS Design-Technology Co-Optimization (DTCO) team sits at the intersection of process technology, design rules, PDK, EDA tools, and circuit design, making sure each new node delivers competitive analog, mixed-signal, and custom-design density, performance, and productivity. The Role: We are seeking a senior technical leader in DTCO to define and drive co-optimization of Intel Foundry's next-generation process technologies for analog, mixed-signal, and custom design. You will identify where technology definition limits design outcomes (density, drive, matching, high-voltage support, layout productivity), quantify the impact, and drive resolution across process, design-rule, PDK, EDA, and design teams. This is a senior individual-contributor role with technical leadership across multiple organizations and external EDA partners. Responsibilities: Lead AMS DTCO for future Intel Foundry nodes: evaluate device architecture, front-end and back-end design rules, metal stack, and patterning choices against analog, mixed-signal, and custom-design requirements. Run a closed-loop DTCO process: sense issues from designers, partners, and test chips; prioritize by PPA and productivity impact; drive rule, PDK, or flow changes; and validate the result on silicon and in design.