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Silicon Roles

Product Failure Analysis Engineer - SCAN Design for Test

IntelUS, Oregon, Hillsboro$141,910+Design for Test
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The published floor of $141,910 is 3% below the Design for Test median of $146,000. First seen on this site 2026-10-07, open 2 days.
Posted 2026-10-06 · read from workday

Job Details: Job Description: At Intel, we create world-changing technology that enriches the lives of every person on earth. As a global leader in semiconductor innovation, we design and manufacture the world's most advanced chips — powering everything from personal computers and smartphones to data centers, AI systems, and autonomous vehicles. Our Oregon campus is one of our most important engineering hubs in the world, home to thousands of brilliant engineers who are shaping the future of technology. We believe that diversity of thought, background, and experience makes us stronger — and we're committed to building a workplace where everyone can do their best work. We are seeking an experienced Product Failure Analysis Engineer - SCAN Design for Test who is excited by the opportunity to help enable the success of Intel Foundry's leading-edge 18A technology. The ideal candidate brings 6-12 years of semiconductor experience with deep expertise in DFT, ATPG, scan diagnosis, and post-silicon debug, along with a proven track record of solving complex silicon issues in advanced process technologies. In this role, you will play a critical part in accelerating the ramp and quality of Intel Foundry products by driving root-cause analysis of silicon failures, partnering across design, test, technology development, and manufacturing organizations to quickly identify and resolve product and process issues. Your technical leadership will directly contribute to improving product quality, yield, reliability, and time-to-market for next-generation foundry customers.