Senior Design Verification Engineer

RESPONSIBILITIES - Define, plan, and implement block and system level verification strategies - Write and review test plans, develop test harnesses and test sequences - Drive the design verification process to successful closure by meeting defined verification metrics across the test plan, functional coverage, and code coverage - Collaborate closely with the Design team to debug, root-cause, and resolve functional failures within the design - Work collaboratively with cross-functional teams, including Design, Model, Emulation, and Silicon Validation, to ensure the highest standards of design quality BASIC QUALIFICATIONS - Bachelor's degree in Electrical Engineering, Computer Science, or a closely related technical field - 5+ years of experience in block and system level verification utilizing SystemVerilog/UVM-based methodologies - Proven experience with Electronic Design Automation (EDA) tools and proficiency in scripting languages (Python, Perl, Shell) for developing verification tools and flows - Experience in architecting and deploying Design Verification infrastructure, including executing the complete verification cycle from planning to closure PREFERRED QUALIFICATIONS - Master’s degree in Electrical Engineering, Computer Science, or a closely related technical field - Expertise in developing UVM-based verification environments from initial setup - Expertise in developing Python-based verification environment such as cocotb - Experience in IP or integration verification for high-speed interfaces such as PCIe, UCIe, UALink, and Ethernet - Experience verifying…