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Silicon Roles

Senior Design Verification Engineer

IntelUS, California, Santa Clara$190,610+Design Verification
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The published floor of $190,610 is 34% above the Design Verification median of $141,910. First seen on this site 2026-11-12, open 1 days.
Posted 2026-11-11 · read from workday

Job Details: Job Description: About the Team Intel is building something new. The Unified Intel Chassis (UIC) team is a new IP development team focused on chassis and interconnect technology and a configurable generator for SoCs and chiplets. As a Senior Design Verification Engineer, you will verify coherent, non-coherent, and I/O-coherent systems — including interactions among interconnects, caches, memory subsystems, and chassis functions such as clocking, power management, reset, debug, and trace. This is a hands-on technical role spanning the full verification lifecycle: from clarifying requirements and building models and checkers through debugging and verification signoff. You will work closely with engineers across architecture, design, verification, and tooling to turn specifications into working, tested hardware. Simulation, formal verification, and AI-assisted development are part of how we work.