Senior Mixed Signal Post Silicon Validation Engineer IOs

Job Details: Job Description: About the Team The Hard IP Development Group (HIPD) within Intel's Central Engineering Organization is responsible for developing leadership IPs that are power-winning products for Server, Client, and Networking SOCs, as well as Intel Foundry Customers. HIPD develops a broad portfolio of Serial and Parallel IO PHYs including PCIe, USB, TypeC, UCIe Die-to-Die, DDR/LPDDR, and Ethernet PHYs. The Electrical Validation and Debug group within HIPD is a dynamic and versatile team of engineers who directly engage with both IP design teams and SOC customers in IP validation and debug for test chips and products. These engineers embody our SOC customer obsession by validating mixed signal IPs and quickly resolving hurdles through hands-on debug. This position is exciting and challenging, offering the opportunity to exercise your mixed signal design, architecture, and post-silicon debug expertise across all HIPD IPs, Client, and Server SOC teams. Position Overview This role focuses on mixed signal high-speed PHY post-silicon validation and debug, spanning IP enabling, customer sighting resolution, and cross-functional collaboration with SOC teams.