Senior Silicon Validation Methodology Engineer - Low Power

NVIDIA Silicon Co-Design Group (SCG) is a wide-ranging, multi-functional team at NVIDIA. We sit at the crossroads of design, architecture, marketing, operations, and productization. Our contributions span from the architecture stage through final product definition. We architect solutions for Datacenter, Server, Gaming, Robotics, Automotive, and Embedded markets. We are fast-paced, collaborative, and focused on making groundbreaking, impactful products. We are seeking a Senior Silicon Validation Methodology Engineer for Low-Power (LPWR). You will own the department LPWR validation methodology across GPU, SoC, and CPU, from architecture to silicon to product. What you'll be doing: Own architecture, design, and first-use of end-to-end LPWR validation methodology from silicon to product, covering corners, edge conditions, variability, and real-world scenarios. Set the department standard for LPWR validation so it is reused across a broad array of silicon products. Define what needs to be tested, why, and how — including coverage bounds, PVT/variability, test-time vs. schedule, signoff criteria, milestone playbooks, and SOL(speed of light) expectations. Invent and land new LPWR validation approaches that go beyond extending an existing test plan. Challenge current paradigms on performance, power, idle vs. active behavior, and corner-case coverage, and drive the resulting methods, tools, and metrics into org default practice. Set LPWR validation strategy and policy across teams, including long-lead items that outlive a single execution cycle.