Senior Silicon Validation Methodology Engineer

NVIDIA Silicon Co-Design Group (SCG) is a wide-ranging, multi-functional team at NVIDIA. We sit at the crossroads of design, architecture, marketing, operations, and productization. Our contributions span from the architecture stage through final product definition. We architect solutions for Datacenter, Server, Gaming, Robotics, Automotive, and Embedded markets. We are fast-paced, collaborative, and focused on making groundbreaking, impactful products. We are seeking a Senior Silicon Validation Methodology Engineer for Clocking and High-Speed I/O (PCIE, USB, MGBE, UFS etc) functional, you will own clocking and HSIO functional validation methodology for the products across GPU/SOC/CPU. What you'll be doing: Own the definition and first-use of clocking and HSIO functional validation methodology from specification through silicon bring-up, covering functional, protocol, SI/PI, clocking behavior, system stability and integration test across corners and real bring-up conditions. Set the standard for validation so it is reused across a broad array of silicon products. Define what needs to be tested, why, and how — including coverage bounds, timing vs. power, signal integrity vs. performance, coverage vs. test time, milestone expectations, and signoff guidance — and turn that into executable concrete test content, pass/fail criteria, and bring-up plans.