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Silicon Roles

Applied ML – Functional Verification Engineer

CadenceSAN JOSE$114,800–$213,200Design Verification
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The published floor of $114,800 is 30% below the Design Verification median of $164,735. First seen on this site 2026-09-22, open 4 days.
Posted 2026-03-06 · read from workday

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Overview Cadence Design Systems Inc. is looking for a motivated and results driven Pre-Silicon Verification Engineer with extensive experience in function verification (formal verification and/or simulation/UVM verification) and a passion for leveraging artificial intelligence to redefine the verification landscape. In this role, you will be p art of the ChipStack AI Super Agent team and will operate at the forefront of semiconductor design and AI innovation, utilizing advanced AI tools to architect, design, and validate the next generation of verification methodologies.