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Silicon Roles

Design Verification Architect / Director

CadenceSAN JOSE$185,500–$344,500Design Verification
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The published floor of $185,500 is 13% above the Design Verification median of $164,735. First seen on this site 2026-09-22, open 4 days.
Posted 2026-09-16 · read from workday

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Location San Jose, CA and Austin, TX Job Description Responsibilities As a Design Verification Team Director, lead and run the Processor Verification team, you will be responsible for the verification of microprocessor cores and their peripherals Relevant experience in-order/out-of-order CPU cores and memory subsystem strongly preferred Crafting verification plans and executing them to verify highly complex CPU designs. You will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will be responsible for coverage collection and closure You will work closely with cross-functional teams (DV/Arch/Design/FW) to identify coverage scope Tracking and reporting the work of 7-10 engineers Required Skills and Experience: 17+ years of design verification experience BS (or higher) in EE/Computer Engineering Proven experience at leading/managing team.