Formal Verification Engineer

Job Details: Job Description: The Role and Impact Intel is seeking a Formal Verification Engineer for the Silicon Chassis team. In this role, you will apply advanced formal methods to rigorously verify interconnect fabrics, protocol bridges, and link-layer logic. You will drive end-to-end formal verification processes, including property specification and proof convergence across multiple protocol domains. Through close collaboration with architecture, design, and software teams, your work will ensure the delivery of high-quality, cutting-edge solutions. Business Group The Central Engineering Group (CEG) focuses on enabling technology innovation across Intel by delivering robust engineering solutions and methodologies. As part of this group, the UIC Validation Transport team plays a critical role in supporting Intel's broader goals of advancing silicon development. By leveraging formal verification techniques, this team ensures the reliability and performance of foundational technologies used in Intel's products worldwide. Key Responsibilities - Develop and execute formal verification test plans, including defining scope, strategies, and methodologies. - Create abstraction models to facilitate convergence on complex designs and apply abstraction techniques for formal analysis. - Generate and validate proofs to verify designs, troubleshoot failing tests, and implement corrective measures. - Collaborate across architecture, RTL design, and physical implementation teams to improve verification accuracy for advanced features.