Lead Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description: AI Design Validation Specialist (Verification / Workflow SME) Role Overview We are seeking an experienced AI EDA Specialist (Verification / Workflow SME) to bridge the gap between semiconductor verification methodologies and AI-driven automation. This role will serve as the domain expert responsible for validating AI-generated verification artifacts, debugging customer verification challenges, developing ground-truth datasets, and ensuring AI solutions align with industry-standard verification workflows. The ideal candidate combines deep expertise in SystemVerilog, UVM, simulation, and formal verification with a passion for enabling next-generation AI-powered engineering solutions. Key Responsibilities Verification Workflow Validation Validate AI-generated outputs across RTL verification workflows. Review and assessment generated: UVM testbenches Assertions (SVA) Coverage strategies Simulation and formal verification flows Ensure compliance with industry-standard verification methodologies and best practices. Customer Technical Support & Debugging Investigate and resolve customer-reported issues involving: UVM environments RTL verification testbenches Functional coverage Assertion failures Simulation regressions Reproduce, analyze, and document root causes of complex verification problems. Partner closely with customers, application engineers, and product teams to drive issue resolution.