Tcl jobs
389 open roles mention Tcl. Median advertised base $157,000 across 75 published ranges.
Principal Physical Design Engineer / Physical Design – ACE US NEW
Nxp · Austin (Oakhill, Office) · 2026-09-25
no range
Lead STA Engineer NEW
Nxp · Bangalore · 2026-09-25
no range
CAD/EDA Tools Automation Engineer NEW
Intel · US, Oregon, Hillsboro · 2026-09-25
$149,600+
Silicon Emulation Engineer
Waymo · Mountain View, CA, USA · 2026-09-25
$175,000+
FPGA Associate (Summer 2027)
Astranis · San Francisco · 2026-09-25
no range
FPGA Associate (Winter 2027)
Astranis · San Francisco · 2026-09-25
no range
FPGA Engineer
Astranis · San Francisco · 2026-09-25
$140,000+
FPGA Intern (Summer 2027)
Astranis · San Francisco · 2026-09-25
no range
FPGA Intern (Winter 2027)
Astranis · San Francisco · 2026-09-25
no range
Senior FPGA Engineer
Astranis · San Francisco · 2026-09-25
$175,000+
Sr/Staff Engineer, Design Verification,System IP NEW
Tenstorrent · Bengaluru, Karnataka, India · 2026-09-25
no range
Sr. Staff Physical Design Engineer
Lightmatter · Boston, MA · 2026-09-25
$217,000+
Sr. Staff Physical Design Engineer
Lightmatter · Mountain View, CA · 2026-09-25
$220,000+
Sr. Staff Physical Design Engineer
Lightmatter · Toronto, ON · 2026-09-25
$191,000+
Staff Engineer, ASIC IP STA NEW
Micron · Bengaluru, India · 2026-09-24
no range
Sr. Manager, Digital Design
Analogdevices · India, Hyderabad · 2026-09-24
no range
Physical design CAD engineer NEW
Marvell · Yokneam · 2026-09-24
no range
Design Verification Intern NEW
Marvell · Petah-Tikva · 2026-09-24
no range
AI/ML Physical Design Flow Engineer
Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · 2026-09-24
no range
Chiplet Physical Design Engineer
Tenstorrent · Santa Clara, California, United States · 2026-09-24
no range
DFT Engineer
Tenstorrent · Santa Clara, California, United States · 2026-09-24
no range
Full-Chip Physical Design Verification Engineer
Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · 2026-09-24
no range
Physical Design CPU Methodology Engineer
Tenstorrent · Santa Clara, California, United States · 2026-09-24
no range
Physical Design Engineer
Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · 2026-09-24
no range
Physical Design Engineer, AI Accelerator IP
Tenstorrent · Austin, Texas, United States; Belgrade, Serbia; Toronto, Ontario, Canada · 2026-09-24
no range
Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)
Tenstorrent · Santa Clara, California, United States · 2026-09-24
no range
Physical Design Engineer, ML4PD
Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · 2026-09-24
no range
Physical Design Engineer - STA
Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · 2026-09-24
no range
Physical Design Engineer, Timing
Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · 2026-09-24
no range
Physical Design Methodology Engineer, AI HW IP
Tenstorrent · Austin, Texas, United States; Belgrade, Serbia; Toronto, Ontario, Canada · 2026-09-24
no range
Senior DFT Engineer, Architecture
Tenstorrent · Tokyo, Japan · 2026-09-24
no range
Sr. Engineer, SoC Design Verification
Tenstorrent · Boston, Massachusetts, United States; Santa Clara, California, United States; Toronto, Ontario, Canada · 2026-09-24
no range
Staff Engineer, Physical Design
Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · 2026-09-24
no range
System IP RTL Design Lead
Tenstorrent · Bengaluru, Karnataka, India · 2026-09-24
no range
Senior ASIC RTL Design Engineer, AI Hardware
Cerebras · Sunnyvale, CA · 2026-09-24
$200,000–$290,000
Principal Design Verification Engineer
indie Semiconductor · Aliso Viejo, CA; Cordoba, Argentina; Toronto, Canada · 2026-09-24
no range
Foundry PDK / Collateral Integration Engineer (CAD/EDA)
Micron · Richardson, TX · 2026-09-23
no range
Senior /Staff AMS Layout engineer-DPG-LPDDR
Micron · Hyderabad - Phoenix Aquila, India · 2026-09-23
no range
Staff Engineer, CAD PD/STA
Micron · Hyderabad - Phoenix Aquila, India · 2026-09-23
no range
Senior Formal Verification Engineer
Nvidia · US, CA, Santa Clara · 2026-09-23
no range
Senior Digital Design Engineer
Analogdevices · India, Hyderabad · 2026-09-23
no range
Senior Digital Design Engineer
Analogdevices · India, Hyderabad · 2026-09-23
no range
Senior Digital Design Engineer
Analogdevices · India, Hyderabad · 2026-09-23
no range
Senior Physical Design Engineer NEW
Intel · US, Oregon, Hillsboro · 2026-09-23
$141,910+
Qubit Control Physical Design Engineer
Intel · US, Oregon, Hillsboro · 2026-09-23
$141,910+
Physical Design for PPA Optimization Engineer
Intel · Israel, Haifa · 2026-09-23
no range
DFT Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
Director, Physical Design
Astera Labs · Hyderabad, Telangana, India · 2026-09-23
no range
Junior Physical Design Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
Lead Emulation Engineer
Astera Labs · Bengaluru, Karnataka, India · 2026-09-23
no range
Manager, Package Design Engineering
Astera Labs · San Jose, California, United States · 2026-09-23
$230,000+
Physical Design Student
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
Principal DFT Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
Principal Emulation Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
Principal Physical Design Engineer
Astera Labs · San Jose, California, United States · 2026-09-23
$185,000–$240,000
Principal Physical Design Engineer -EMIR & Power Integrity
Astera Labs · San Jose, California, United States · 2026-09-23
$185,000–$240,000
Principal Physical Design Engineer, Methodology
Astera Labs · San Jose, California, United States · 2026-09-23
$185,000–$240,000
Principal Physical Design Engineer, STA
Astera Labs · San Jose, California, United States · 2026-09-23
no range
Principal Product Application Engineer - PCIe
Astera Labs · San Jose, California, United States · 2026-09-23
$170,500–$220,000
Principal Product Applications Engineer - Ethernet
Astera Labs · San Jose, California, United States · 2026-09-23
$158,400–$230,000
Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet
Astera Labs · San Jose, California, United States · 2026-09-23
$185,000–$230,000
Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet
Astera Labs · Taipei, Taiwan · 2026-09-23
no range
Senior Design Verification Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
Senior Emulation Engineer
Astera Labs · Israel · 2026-09-23
no range
Senior Engineer PD
Astera Labs · Singapore, Singapore · 2026-09-23
no range
Senior STA Engineer
Astera Labs · Ahmedabad, Gujarat, India · 2026-09-23
no range
Senior/ Staff Front-End CAD Engineer
Astera Labs · Israel · 2026-09-23
no range
Senior/ Staff Physical Design Engineer
Astera Labs · Haifa District, Israel · 2026-09-23
no range
Staff DFT Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
Staff Physical Design Engineer - SoC EMIR Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
Staff/ Principal Design Verification Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
Staff/ Principal Physical Design CAD Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
Staff/ Principal Physical Design Engineer - SoC EMIR Expert
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
Staff/ Principal Physical Design STA Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel · 2026-09-23
no range
STA Physical Design Engineer, Senior Principal
Astera Labs · San Jose, California, United States · 2026-09-23
no range
Tech Lead ASIC Design Engineer
Astera Labs · Bengaluru, Karnataka, India · 2026-09-23
no range
Tech Lead, Formal Verification
Astera Labs · Bengaluru, Karnataka, India · 2026-09-23
no range
Tech Lead, Physical Design
Astera Labs · Bengaluru, Karnataka, India · 2026-09-23
no range
Tech Lead, STA
Astera Labs · Hyderabad, Telangana, India · 2026-09-23
no range
Technical Lead Physical Design Engineer
Astera Labs · Toronto, Ontario, Canada · 2026-09-23
$140,000+
Senior DFT Engineer
Nvidia · US, CA, Santa Clara · 2026-09-22
no range
Physical Design and Timing Engineer Intern - Summer 2027
Nvidia · US, CA, Santa Clara · 2026-09-22
no range
Principal Engineer, Design Verification Engineering
Analogdevices · India, Bangalore, RMZ · 2026-09-22
no range
Digital Verification Engineer
Analogdevices · China, Shanghai, Pudong, ZuChongzhi · 2026-09-22
no range
Digital Verification Engineer
Analogdevices · China, Beijing, Haidian, Xixiaokou · 2026-09-22
no range
Digital Design Engineer
Analogdevices · China, Beijing, Haidian, Xixiaokou · 2026-09-22
no range
Digital Design Engineer
Analogdevices · China, Shanghai, Pudong, ZuChongzhi · 2026-09-22
no range
Digital Verification Engineer
Analogdevices · China, Beijing, Haidian, Xixiaokou · 2026-09-22
no range
Digital Design (Physical) Engineer
Analogdevices · China, Beijing, Haidian, Xixiaokou · 2026-09-22
no range
Digital Design Engineer
Analogdevices · Singapore, Kallang · 2026-09-22
no range
Lead digital verification engineer
Nxp · Bangalore · 2026-09-22
no range
Stage Ingénieur : Conception Numérique SoC - Design for Test (F/H)
Nxp · Caen · 2026-09-22
no range
Stage Ingénieur : Conception pour le test (DFT) / Conception numérique (F/H)
Nxp · Sophia-Antipolis (Valbonne) · 2026-09-22
no range
Sr Staff DFT Engineer
Globalfoundries · IND - Karnataka - Bengaluru - North · 2026-09-22
no range
E-core CPU Physical Design Engineer
Intel · Malaysia, Penang · 2026-09-22
no range
E-core CPU Physical Design Engineer
Intel · Malaysia, Penang · 2026-09-22
no range
Design Verification Engineer
Analogdevices · India, Hyderabad · 2026-09-21
no range
Design Verification Engineer
Analogdevices · India, Hyderabad · 2026-09-21
no range
Senior Design Verification Engineer
Analogdevices · India, Hyderabad · 2026-09-21
no range
Senior Design Verification Engineer
Analogdevices · India, Hyderabad · 2026-09-21
no range
Senior Design Verification Engineer
Analogdevices · India, Hyderabad · 2026-09-21
no range
FPGA and Emulation Prototyping Engineer - MCU
Nxp · Catania · 2026-09-21
no range
Senior Digital Design Engineer - MCU
Nxp · Catania · 2026-09-21
no range
Analog Circuit Design Engineer
Intel · India, Bangalore · 2026-09-21
no range
Senior FPGA Engineer
indie Semiconductor · Cordoba, Argentina; Buenos Aires, Argentina; Toronto, Canada · 2026-09-21
no range
Senior ASIC Design Engineer - DFT
Nvidia · US, CA, Santa Clara · 2026-09-18
no range
Senior DFT Methodology Engineer
Nvidia · US, CA, Santa Clara · 2026-09-18
no range
Senior AI STA Engineer, Sub-chip
Nvidia · Israel, Yokneam · 2026-09-18
no range
Staff Engineer – DFT Engineering
Analogdevices · India, Bangalore, RMZ · 2026-09-18
no range
Director, Digital Design
Analogdevices · India, Bangalore, RMZ · 2026-09-18
no range
Senior DFT Engineer
Nvidia · US, CA, Santa Clara · 2026-09-17
no range
Senior ASIC Physical Design Engineer, Netlisting
Nvidia · US, CA, Santa Clara · 2026-09-17
no range
Senior Circuit Silicon Correlation DFT Engineer
Nvidia · India, Bengaluru · 2026-09-17
no range
DFT Engineer
Nxp · Tianjin (Teda) · 2026-09-17
no range
Principal Analog/Mixed Signal CAD Engineer
Marvell · Santa Clara, CA · 2026-09-17
no range
Design For Test Intern, MS - Summer 2027
Marvell · Santa Clara, CA · 2026-09-17
no range
ECAD PCB Tools Developer
Nvidia · US, CA, Santa Clara · 2026-09-16
no range
Senior DFT - Silicon Validation Engineer
Nvidia · US, CA, Santa Clara · 2026-09-16
no range
Senior EDA Engineer, SOC Design Methodology
Nvidia · US, CA, Santa Clara · 2026-09-16
no range
Senior Engineer, FPGA Design
Analogdevices · Romania, Cluj-Napoca · 2026-09-16
no range
Principal Analog Mixed Signal Verification Engineer
Nxp · Chandler (Office) · 2026-09-16
no range
Principal Physical Design Engineer - MCU
Nxp · Catania · 2026-09-16
no range
Senior Lead Verification Engineer, Digital IP
Nxp · Bangalore · 2026-09-16
no range
Senior Principal Digital Design Engineer
Cadence · SAN JOSE · 2026-09-16
$154,000–$286,000
Back End( BE) Process Integration Engineer
Intel · US, Oregon, Hillsboro · 2026-09-16
$103,730+
Intern - HBM SoC Physical Design Engineer
Micron · Folsom, CA · 2026-09-15
no range
Custom SOC IP Verification Engineer
Nvidia · US, CA, Santa Clara · 2026-09-15
no range
Physical Design Engineer (RDSS Intern)
Nvidia · Taiwan, Hsinchu · 2026-09-15
no range
Engineer, Digital Design Engineering
Analogdevices · Spain, Valencia, Cortes Valencianas · 2026-09-15
no range
Senior Engineer, Design Verification Engineering
Analogdevices · China, Shanghai, Pudong, ZuChongzhi · 2026-09-15
no range
Senior IC Design Verification Engineer
Nxp · Kanata · 2026-09-15
$110,600–$152,000
Internship: Digital Design F/M
Nxp · Catania · 2026-09-15
no range
Lead Verification Engineer
Cadence · BANGALORE · 2026-09-15
no range
Timing & Power Analysis CAD Engineer
Marvell · Bangalore · 2026-09-15
no range
DFT Engineer
Graphcore · Bristol, UK; Cambridge, UK · 2026-09-15
no range
Logical Design Engineer
Graphcore · Bristol, UK; Cambridge, UK · 2026-09-15
no range
Principal SLT Test Engineer
Graphcore · Austin, Texas, United States · 2026-09-15
no range
Senior Physical Design Engineer - Bengaluru, Multiple Vacancies
Graphcore · Bengaluru, India · 2026-09-15
no range
Senior Silicon Logical Design Engineer - Bengaluru
Graphcore · Bengaluru, India · 2026-09-15
no range
Senior SLT Test Engineer
Graphcore · Austin, Texas, United States · 2026-09-15
no range
Silicon Physical Design Engineer
Graphcore · Bristol, UK; Cambridge, UK · 2026-09-15
no range
Staff Silicon Logical Design Engineer - Bengaluru, Multiple Vacancies
Graphcore · Bengaluru, India · 2026-09-15
no range
Staff Silicon Physical Design Engineer - Bengaluru
Graphcore · Bengaluru, India · 2026-09-15
no range
Staff SLT Test Engineer
Graphcore · Austin, Texas, United States · 2026-09-15
no range
Custom SOC IP Verification Engineer
Nvidia · US, CA, Santa Clara · 2026-09-14
no range
Senior Engineer, Design Verification Engineering
Analogdevices · Egypt, New Cairo · 2026-09-14
no range
Digital Verification Engineer - MCU
Nxp · Catania · 2026-09-14
no range
Senior DFT Logic Design Engineer
Intel · US, Arizona, Phoenix · 2026-09-14
$141,910+
RTL Design Engineer
Intel · US, Texas, Austin · 2026-09-14
$91,150+
Analog Design Intern, MS - Summer 2027
Marvell · Santa Clara, CA · 2026-09-14
no range