Physical Verification Engineer

NVIDIA is seeking a Physical Verification Engineer to help ensure our ASIC and SoC designs are clean, correct, and ready for tapeout. This role focuses on physical verification quality across layout data, connectivity, and manufacturing rule compliance. You will work closely with physical design, custom layout, and methodology teams to run verification flows, debug issues, and improve signoff robustness. This is an excellent opportunity for an engineer who enjoys detailed analysis and high-impact signoff work. What you’ll be doing: Run and analyze physical verification checks such as DRC, LVS, and other tapeout-quality signoff checks. Debug physical verification violations and partner with design teams to drive clean closure. Review layout, netlist, and runset interactions to identify root causes and recommend fixes. Support full-chip and block-level verification readiness across implementation milestones. Improve physical verification flow quality, turnaround time, and automation. Collaborate with methodology, CAD, and foundry-facing teams on rule interpretation and signoff quality. What we need to see: B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience. 2+ years of experience in physical verification, backend implementation, or VLSI signoff. Strong understanding of DRC, LVS, antenna, and layout verification concepts. Hands-on experience with tools such as Calibre, ICV, Pegasus, or equivalent physical verification tools. Ability to debug verification issues across layout, extracted views, and netlist connectivity.