Principal Digital RTL Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Principal Digital RTL Engineer Location: San Jose, CA (Onsite) Role Overview As a Principal Engineer on our Analog/Mixed-Signal (AMS) Design team, you will architect and deliver the high-performance analog building blocks at the heart of Astera Labs' purpose-built connectivity silicon. From high-speed SerDes and PLLs to data converters and precision references, your circuits will directly enable the bandwidth, signal integrity, and power efficiency that rack-scale AI infrastructure demands. This is a hands-on technical leadership role at a hyper-growth company defining the connectivity backbone of the AI era.