Principal Digital Verification Engineer

Job Title: Principal Digital Verification Engineer Primary Location: Chandler, Arizona, USA Role Summary: The Advanced Power Systems group within NXP’s Power and Energy Business Line is seeking a Senior Digital Verification Engineer to develop next-generation Power Management ICs (PMICs) for automotive and industrial applications. This role will lead digital verification from architecture review through verification signoff, ensuring functionality, quality, reliability, and compliance. Job Responsibility: Lead digital verification activities and drive successful project execution from planning through signoff. Define verification plans, methodologies, environments, regressions, coverage goals, and signoff criteria. Review product requirements, architecture specifications, microarchitecture, interfaces, and implementation plans. Develop and maintain advanced verification environments using SystemVerilog, UVM, VIPs, scoreboards, monitors, checkers, and assertions. Create directed and constrained-random test scenarios to validate functionality, performance, robustness, and corner-case behavior. Define, implement, and analyze functional, code, and assertion coverage; drive coverage closure and signoff. Apply SystemVerilog Assertions (SVA), formal verification methodologies, and regression analysis to identify and resolve issues. Verify PMIC digital control, telemetry, diagnostics, safety, power sequencing, fault management, communication interfaces, and embedded control functions.