Senior Digital Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. This strategy is supplemented by AI-augmented development practices throughout all our organizations to empower our team to focus on creative problem-solving and innovation. Our customers are the world’s most innovative companies, delivering extraordinary electronic products—from chips to boards to systems—for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health. Join us and be part of a culture that values innovation, collaboration, and customer success. At Secure-IC, a Cadence company, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: T4 - Principal Design Engineer Location: France, Rennes (preferably) or Paris Reports to: Sr Design Engineering Manager Job Overview: Senior Digital Verification Engineer You will lead the development and execution of robust, reusable UVM verification environments for our products, ensuring functional ‑ coverage and first ‑ silicon success. By driving verification strategy, automating large ‑ scale regression flows, and mentoring the verification team, the role directly safeguards the quality of high ‑ performance ASIC designs.