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Silicon Roles

Senior Director, AI SOC Design Verification

IntelUS, California, Santa Clara$256,050+Design VerificationASIC & SoC Architecture
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The published floor of $256,050 is 55% above the Design Verification median of $164,735. First seen on this site 2026-09-22, open 4 days.
Posted 2026-04-10 · read from workday

Job Details: Job Description: Directs and manages a team of design verification engineers responsible for Subsystem and SoC design verification. Deploys and manages leading silicon design verification processes, procedures, verification tools, and technologies based on latest best industry practices. Works with design, microarchitecture, and postsilicon validation teams to identify design bugs and improve overall microarchitecture. Collaborates with program leaders on the verification delivery and regression metrics against milestone requirements. Understands security milestone expectations and works with SoC security validation teams to incorporate security related testing through validation, hackathon reviews, and new validation techniques to improve security coverage. Executes security and security development lifecycle tasks per job role and schedule milestones. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment. Qualifications: Education: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, or a related field. Experience: Typically 15+ years in ASIC/SoC design and verification. 5-10+ years of experience in formal people management or leadership roles. Technical Expertise: Expert-level command of SystemVerilog and UVM.