Silicon Validation Engineer

NVIDIA Silicon Co-design Group is seeking a versatile engineer to join the HW ArchDev Methodology team. SCG operates across the full product lifecycle—from early architecture definition through silicon bring-up to production—providing a unique end-to-end perspective on next-generation systems You define how validation is done. Not how it's been done, how it should be done, for chips that don't exist yet. NVIDIA's HW ArchDev Methodology team sits at a rare intersection: architecture, silicon bring-up, and production, all in one group. We build the validation strategies, automation frameworks, and telemetry systems that determine whether next-generation GPUs and AI accelerators ship on time and at quality. The problems are novel. The stakes are real. What you’ll be doing: Design system-level validation strategies for complex architectures, corner cases, PVT, large-scale behavior, feature interactions Build AI-assisted and data-driven validation workflows that improve coverage, debug turnaround, and efficiency Profile real workloads: training, inference, HPC, video, and emerging applications Deploy automation and telemetry pipelines that scale across products and teams Drive silicon bring-up and root-cause debug with reusable, high-leverage methods What we need to see: BS/MS in EE/CE (or equivalent experience) 4+ years in silicon bring-up, ASIC validation, or system-level debug Grounding in PVT, timing (STA), signal integrity, power, and high-speed IO (PCIe, chip-to-chip) Understanding of firmware/driver-hardware interaction Experience or curiosity around data-driven…