SoC Compute/Memory Subsystem Architect

Job Details: Job Description: About the Role The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems. We are seeking a Senior SoC Compute & Memory Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms. This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments. What You’ll Do Key responsibilities will include but not limited to: Cache Hierarchy and Coherency Architecture 1. Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache). 2. Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions). 3. Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity. Memory Subsystem Architecture 1.