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Silicon Roles

SoC Validation Engineer – Power Management

IntelUS, California, Folsom$164,470+ASIC & SoC Architecture
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The published floor of $164,470 is exactly at the ASIC & SoC Architecture median of $165,000. First seen on this site 2026-11-07, open 6 days.
Posted 2026-11-06 · read from workday

Job Details: Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. The Role and Impact: Intel is seeking a motivated and experienced SoC Validation Engineer to join our Power Management Validation team. In this role, you will be responsible for validating power management architectures and features that enable Intel's next-generation products. You will play a critical role in ensuring design quality, functionality, and power efficiency by developing innovative validation strategies, executing comprehensive test plans, and driving debug activities across complex SoC designs. As a SoC Power Management Validation Engineer, you will work closely with architecture, design, and verification teams to validate key power management features including Dynamic Voltage and Frequency Scaling (DVFS), power gating, clock gating, reset flows, low-power states, thermal management, and telemetry.