Sr Principal Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Qualifications Minimal qualification requires BS/MS degree EE or CS with [ 5-7+ years (T4) ] of experience in relevant experience. As a [Principal Verification Engineer (T4) ] you will be responsible for scheduling, designing, developing, and supporting UVM-based verification environments, processes, and methodologies for IP models of system level memory such as SDRAM ( LPDDRx , DDRx , HBMx ), DFI PHY, UFS, and complex storage memory models for use on hardware-based verification products. · Must analyze customer & vendor protocol requirements and execute on highly complex verification projects from requirements through delivery to post-delivery support. · Must analyze product-wide feature requirements and execute on their verification. · Must integrate additional related tools and processes—including coverage, reporting, and regressing—to build a robust team-level verification structure and competence. Additional responsibilities include the following: · Researching tools, languages, methodologies and prototype processes to enhance product verification as well as to demonstrate product quality. · Updating, enhancing, maintaining, and supporting existing system level UVM test environments for memory model products. · Supporting product (IP Library) regression, OS compliance, process automation, and product release preparation as needed.