Substrate Packaging Defect Metro Tool Owner

Job Details: Job Description: We are seeking a motivated and skilled engineer to join our SPTD Yield team as a Defect Metrology Engineer. In this role, you will help drive innovation in EMIB-T, glass core, EMIB scaling, and panel-level packaging technologies for substrate as well as assembly test mfg (ATM) factories for Intel's IPG and IFS customers. Our goal is to be the supplier of choice for advanced, cost-effective substrate packaging by developing leading-edge systems, process capabilities, and inspection technologies to achieve top yields. Join us on our mission to make Intel a great workplace and industry leader. Responsibilities included but not limited to the following: Use defect inspection tools to detect and resolve process issues, collaborating with defect reduction, process integration, and module teams to improve yield. Apply real-time data analysis, reporting, and DOE summaries to guide improvements and decision-making. Maintain flexibility and adaptability to support the evolving demands in Yield space, responding to new challenges and requirements as they arise. Direct next-generation tool installation, reaching major milestones-purchase-spec development, source inspection, design, pre-fac, Safety level approval, Supplier qual, Intel qual, etc.-by collaborating with diverse stakeholders. Demonstrate the ability to manage work independently, proactively identifying and resolving issues with minimal supervision, and providing leadership in defect metrology and Yield enhancement initiatives.