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Director, SoC Design Engineering

IntelUS, California, Santa Clara$220,920+ASIC & SoC Architecture
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The published floor of $220,920 is 34% above the ASIC & SoC Architecture median of $165,000. First seen on this site 2026-09-22, open 5 days.
Posted 2026-06-04 · read from workday

Job Details: Job Description: The Role and Impact We are seeking a highly experienced a Director, SoC Design Engineering, to lead the functional verification efforts for cutting-edge system-on-chip (SoC) designs. In this strategic role, you will define and implement scalable and reusable verification methodologies that ensure first-pass silicon success. As a trusted domain expert, you will directly influence Intel's technical direction, mentor the next generation of engineers, and drive innovation that strengthens Intel's leadership in the semiconductor industry. This position offers a tremendous opportunity to shape the quality and performance of Intel products, ensuring they meet and exceed the expectations of customers worldwide. Key Responsibilities - Architect and define end-to-end SoC verification strategies, including simulation, emulation, and formal verification approaches, to validate complex SoC designs. - Develop and execute block, subsystem, and SoC-level verification plans, including test benches and coverage models, to ensure compliance with microarchitecture specifications. - Lead verification closure for critical interfaces, including AXI, ACE, CHI, and interconnect fabrics. - Collaborate with SoC architects, RTL designers, and firmware teams to define verification hooks, assertions, and coverage metrics. - Oversee the integration of multiple IPs such as PCIe Gen6/7, DDR5/6, and Ethernet into the SoC environment, driving verification success.