Hardware Engineer, DFT

NORMAL COMPUTING | BUILD WITH US Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London. THE ROLE Hybrid: 3 days a week in the office, in Mountain View, New York or London. As a Design-for-Test (DFT) Engineer at Normal, you will own the DFT architecture and implementation for our next-generation, physics-inspired ASICs, from early RTL design through tapeout and silicon bring-up. You will define and drive scan/ATPG, memory built-in self-test (MBIST), and boundary-scan strategies, working closely with RTL, verification, physical design, and silicon product engineering teams. This is a hands-on technical leadership role with end-to-end ownership of silicon testability. You will establish DFT methodologies, guide external implementation partners, and ensure our designs are ready for manufacturing test. You’ll work on unconventional computing architectures where testability must be considered from the beginning, with the opportunity to shape the DFT infrastructure for an entirely new class of silicon. WHAT YOU WILL OWN - DFT Architecture: Define and own chip-level DFT architecture, including scan insertion, ATPG, scan compression, MBIST, boundary scan/JTAG, and test access infrastructure.