Lead Logic Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Lead Logic Design Engineer Experience 6-10 years Job Summary We are seeking a Lead Logic Design Engineer with deep expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The candidate will provide technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up. Key Responsibilities Lead RTL/microarchitecture development for complex connectivity IP/subsystems . Translate specifications and system requirements into robust hardware architecture. Design high-performance and scalable logic for controllers/subsystems. Work across connectivity IP / subsystem layers including Transaction, Data Link, and Physical interface integration as applicable to the role. Develop and review RTL using SystemVerilog/Verilog .