Lead Logic Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Lead Logic Design Engineer – UALink IP/Subsystem Experience 6–10 years Job Summary Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design. Key Responsibilities Lead UALink IP/subsystem RTL development. Translate protocol requirements into detailed microarchitecture. Design high-performance control and data-path logic. Work on buffering, arbitration, flow control, ordering, and error handling. Develop and review SystemVerilog RTL. Drive performance, area, power, and latency optimization. Collaborate with verification, SoC integration, and physical design teams. Debug complex functional and integration issues. Review RTL and mentor engineers. Support silicon debug and issue resolution.