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Silicon Roles

Principal AE (STA - SignOff)

CadenceAUSTIN$116,200–$215,800Physical Design
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The published floor of $116,200 is 25% below the Physical Design median of $154,000. First seen on this site 2026-10-15, open 29 days.
Posted 2026-11-02 · read from workday

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for a Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. The candidate will work closely with sales executives in supporting sales campaigns by delivering workshops, benchmarks, product demonstrations, methodology consultations and product support. Position also involves: • Presenting to customers the technical capabilities of Cadence Digital Implementation and Signoff tools and flows (Synthesis, Place and Route, Timing/Physical/Power Signoff). • Recognizing opportunities for products at existing customers or potential customers, and working with account team to define and execute technical campaigns • Support technical evaluations/benchmarks and drive the process to deliver Cadence solutions implementations • Ongoing support and usage proliferation at existing customers (on/offsite) • Working closely with R&D on tools and methodology improvements • Create and contribute technical content for Cadence Online Support • Travel as required (up to 20%) The Position Requirements are … Minimum BS-EE plus 8 to 10 year’s experience or MS-EE, plus 6 to 8 year’s experience, Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions Digital Design Fundamentals, Semiconductor fundamentals and Static Timing Analysis is required Experience with ASIC digital implementation flows and tools Working…