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Silicon Roles

Principal Digital Design Engineer (AI Fabric)

Astera LabsSan Jose, CA$185,000+RTL Design
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The published floor of $185,000 is 6% above the RTL Design median of $175,000. First seen on this site 2026-08-10.
Posted 2026-07-31 · read from greenhouse

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high performance products in a fast-paced, collaborative environment. Key Responsibilities Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design. Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues. Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.