Principal Logic Design Engineer - UALink IP/Subsystem

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Principal Logic Design Engineer – UALink IP/Subsystem Experience 10–15 years Job Summary We are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems . Key Responsibilities Lead architecture and RTL development for UALink IP/subsystems. Translate protocol and system requirements into scalable hardware architecture. Design high-bandwidth, low-latency data paths and control logic. Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability . Define interfaces between UALink and other SoC/interconnect components. Develop and review SystemVerilog RTL. Drive design optimization for performance, power, area, and latency.