Senior Digital/AMS Validation and Integration Engineer

We are seeking a Senior Digital/AMS Design Engineer to drive the integration of complex digital logic into our industry-leading Automotive SerDes transceivers. In this role, you will be responsible for the RTL design of the "Digital-Analog Wrapper," ensuring seamless control and data flow between high-speed analog front-ends and the DSP/Link-layer logic. You will own the path from RTL through timing closure and support the validation of that logic in the lab. Key Responsibilities RTL Design & Integration: Develop and integrate RTL (Verilog/SystemVerilog) for control loops, calibration engines, and high-speed data paths in 10G+ transceivers. Mixed-Signal Interface: Define and implement the digital interface for analog blocks (ADCs, PLLs, Driver stages), ensuring robust signal crossing between asynchronous domains. Timing Closure & Synthesis: Lead the digital implementation flow, working closely with the physical design team to achieve timing closure in high-speed clock domains. Silicon Validation: (40% Lab Focus) Partner with the validation team to bring up silicon. Use Python-based tools to exercise RTL features, debug state machines, and verify registers (CSRs) in real-time hardware. Functional Correctness: Execute block-level and chip-level simulations to ensure digital control logic correctly handles analog PVT variations and startup sequences. Skills & Qualifications Education: BSEE/MSEE with 5–8+ years of experience in Digital RTL Design or Digital Integration. HDL Expertise: Advanced proficiency in SystemVerilog/Verilog for synthesis.