Senior SoC Physical Layout & Full-Chip Integration Engineer

Job Details: Job Description: About the Role Join the Design Technology Platform (DTP) organization within Intel Foundry and help drive the development of the methodologies, physical layouts, and silicon platforms that enable next-generation semiconductor technologies. As a member of the X-Chip Full-Chip Integration team, you will play a key role in developing custom layout methodologies, leading full-chip physical integration, and driving physical verification and tapeout execution for advanced testchip and silicon lead vehicles on cutting-edge process technologies. This role is ideal for engineers who have a passion for custom layout design, advanced-node physical design methodologies, and solving complex physical integration challenges. You will work at the intersection of technology development, physical design, verification, and manufacturing, collaborating with experts across Intel Foundry to enable future process technologies and silicon solutions. What You'll Do Responsibilities include, but are not limited to: Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles. Develop and enhance custom layout methodologies and physical design flows. Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance. Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.