Senior SoC Verification/Validation Engineer

Astera LabsSan Jose, CA$165,000+ASIC & SoC Architecture

SystemVerilog Verilog PCIe SerDes Ethernet Python Tape-out

The published floor of $165,000 is 6% below the ASIC & SoC Architecture median of $175,000. First seen on this site 2026-08-10.

Posted 2026-07-31 · read from greenhouse

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are looking for Senior SoC Verification/Validation Engineer who are passionate about bringing next-generation SoCs to life on industry-leading emulation platforms. You will play a critical role in validating complex SoCs for AI connectivity and cloud infrastructure, ensuring functionality and performance well before silicon tape-out.