Senior Static Timing Analysis (STA) Engineer

Job Details: Job Description: Shape the Future of Computing at Intel Intel is seeking an experienced Senior Static Timing Analysis (STA) Engineer to help drive the development of next-generation semiconductor products. In this role, you will play a critical part in delivering high-performance, power-efficient System-on-Chip (SoC) designs that power industry-leading technologies. You will work across architecture, logic design, clocking, DFT, and physical design teams to ensure successful timing convergence, signal integrity, performance optimization, and product readiness. This position offers an exciting opportunity to solve complex engineering challenges while influencing methodologies and best practices used across advanced SoC programs. Key Responsibilities but not limited to: Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements. Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs. Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency. Define methodologies to produce high-quality timing models and enable efficient physical design execution. Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans, and binning strategies. Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.