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Silicon Roles

Technical Lead Digital Design Engineer

Astera LabsSan Jose, California, United States$160,000+RTL Design
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The published floor of $160,000 is 1% below the RTL Design median of $162,250. First seen on this site 2026-11-03, open 7 days.
Posted 2026-11-02 · read from greenhouse

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview Join our team as Technical Lead Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment. Key Responsibilities Own the RTL implementation of complex digital designs from micro-architecture through sign-off. Collaborate with verification teams to review test plans and debug issues. Support efforts to achieve timing closure and implement Design-for-Test (DFT) features. Scripting and automation for ASIC methodology improvement.