Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII. This role demands deep expertise in full physical design flow with a specific focus on closing high-speed D2D interfaces for multi-die/chiplet architectures. This role is remote role open to any location in the U.S. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts. Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off.