Principal DFT Engineer

We are looking for a Principal HW DFT Engineer who will architect, implement, and validate in-vehicle networking devices as part of NXP’s Automotive grade products. You will be responsible for advanced test strategies and implementation, verification and validation of pre/post tapeout of DFT features, overall test coverage improvements, and work closely with RTL and physical team on DFT timing constraints and closures. Main Job Tasks and Responsibilities: Architecture & Strategy: Define and implement advanced DFT strategies, including Scan Architecture, JTAG, Memory BIST (MBIST), and Logic BIST (LBIST) Implementation & Verification: Lead the integration of digital subsystems, perform scan insertion, and generate ATPG (Automatic Test Pattern Generation) patterns while ensuring high fault coverage. Silicon Support: Drive post-silicon validation and debug activities to root cause failures and improve manufacturing test efficiency. Collaboration: Coordinate with physical design and test engineering teams to ensure timing closure and that test patterns are operational immediately upon silicon arrival. Minimum Required Qualifications Education: B.S./M.S.