Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network and last-level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on micro-architecture definition and feasibility. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you'll be doing: As a member of our CPU team, you'll be responsible for synthesis and achieving timing, area, performance and power goals of the on-chip interconnect network and last-level caches. Help evaluate the physical design for next-generation Nvidia coherent interconnects and system-level caches. What we need to see: Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience. 5+ years of experience in processor or other related high-performance semiconductor designs. Physical design expertise in high-frequency design, including hands-on synthesis experience, timing analysis, floor-planning and in-depth knowledge of industry standard physical design tools is required. Experience in interconnect/cache/core design is desirable.