Senior Principal Digital Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Overview As a Senior Principal Digital Design Engineer, you will be responsible for the design, development, and ongoing support of system-level memory IP models used in hardware-based verification products. You will work across a broad range of memory technologies and interfaces, including SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS. In addition to developing new memory models, you will maintain and enhance existing products to ensure performance, quality, usability, and long-term customer support. This role is a highly collaborative individual-contributor position that requires strong RTL design and verification expertise, excellent debugging skills, and the ability to work directly with internal and external customers on complex emulation, simulation, and verification challenges. Key Responsibilities Design, develop, verify, and productize system-level memory IP models for hardware-based verification platforms. Develop memory models supporting technologies and interfaces such as LPDDR, HBM, NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS. Maintain, enhance, debug, and support existing memory IP products throughout their lifecycle. Develop high-quality RTL using Verilog/SystemVerilog, applying sound design and coding practices. Develop and execute verification strategies using industry-standard simulation and emulation tools and methodologies.