Senior SOC Design For Test Engineer

Job Summary NXP Semiconductors is seeking an experienced and motivated Senior Design For Test (DFT) Engineer to join the AI and Chip Engineering (ACE) team. In this role, you will define, implement, verify, and support advanced DFT solutions for complex SoC products developed in leading-edge semiconductor technologies for Automotive and Industrial applications. Working closely with design, verification, product engineering, and manufacturing teams, you will contribute to the delivery of cost-effective, high-quality DFT architectures and manufacturing test solutions that ensure robust product quality and test coverage. Key Responsibilities Define and implement Digital Design For Test (DFT) architectures and solutions at IP, subsystem, and SoC level based on product requirements and specifications. Develop and integrate DFT features including Scan, ATPG, Memory BIST, Logic BIST, JTAG, and related test structures. Align DFT implementation across SoC platforms and IP blocks to ensure efficient, scalable, and high-quality test solutions. Develop and execute ATPG patterns to achieve target fault coverage for Stuck-At, Transition Delay, Memory BIST, and Logic BIST testing. Perform DFT verification, simulations, and validation activities to ensure the correctness and effectiveness of implemented test solutions. Collaborate with design, verification, physical design, and product engineering teams throughout the development cycle to ensure testability requirements are met.